A SoC based low power 8-bit flash ADC in 45 nm CMOS technology

In modern VLSI design the transistor sizing and scaling has an considerable impact. There are very essential two constrains, which needs serious attention to the VLSI chip designer are high speed and low power consumption. Therefore in this paper an 8-bit 3 Gs/sec flash analog-to-digital converter (ADC) in 45nm CMOS technology is presented for low power and high speed system-on-chip (SoC) applications. This low power 8-bit flash Analog to Digital converter comprises 255 comparators and one thermometer to binary encoder. This flash ADC design is an extended research work of the earlier work related to ADC design using CMOS process technology. The schematic simulation of ADC is done in Tanner-Spice Pro (SEdit) and layout simulation is done in Tanner-Spice Pro (L-Edit) V.15.14. The Simulated result shows the power consumption in Flash ADC is 41.78 w. The Threshold Inverter Quantization (TIQ) technique is proposed to get WPMOS/WNMOS < 1 for transistors to keep the power consumption as low as possible. It is also observed that the ADC consumes 41.78 W of peak power and 6.45 W of average power at full speed while it operates on a power supply voltage of 0.6V. Compared with the earlier work, this project consumes less power and high speed with proposed TIQ technique gives an edge in SoC based VLSI design.